1. Field of the Invention
This invention relates to a method of manufacturing semiconductor integrated circuit interconnect structures. The invention relates more particularly to a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, or chromium oxide, fabricated by the method.
2. Background of the Invention
Semiconductor integrated circuit devices typically comprise silicon and multiple layers of vertically stacked metal interconnect layers with dielectric materials disposed between the metal layers. The fabrication of such devices typically involves the repeated deposition or growth, patterning, and etching of thin films of semiconductor, metal, and dielectric materials. Multiple metallization layers are employed to accommodate higher densities as device dimensions shrink to sub-micron levels and dielectric materials are utilized to separate the metallization, or conductive, regions. Contact openings are formed in the dielectric overlying a substrate region to provide conductive pathways to a source, drain and gate regions from a first metal layer. Via openings are formed in subsequent inter-level dielectric (ILD) layers separating various metal layers to provide conductive pathways between the metal layers.
A passivation layer is often deposited over a top metal layer as an insulation and protection layer to prevent mechanical and chemical damage during assembly and packaging. To deposit the passivation layer, the wafer surface may be backsputtered, if needed, and one or two layers of inorganic silicon oxide and/or silicon nitride and/or silicon oxynitride is deposited by chemical vapor deposition. The passivation layer typically has 4000 xc3x85 of silicon oxide and 3000 xc3x85 of silicon nitride, or 10000 xc3x85 of silicon oxide, where 4000 xc3x85 is etched back, and 3000 xc3x85 of silicon nitride. Other common passivation layers have a single coating of 3000 xc3x85 of silicon nitride. An organic spin-on dielectric, such as polyimide, is also sometimes used on top of the inorganic dielectric to form the passivation layer.
One common metal used for forming metal lines, or wiring, on a wafer is aluminum. Aluminum is relatively inexpensive, has a low resistivity, and is relatively easy to etch. Aluminum has also been used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of the via, or contact holes, is decreased to sub-micron levels, a step coverage problem occurs, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers. The poor step coverage in the sub-micron vias results in high current density and enhances electromigration, which is the transport of metal ions through conductors resulting from passage of direct electrical current.
Metals, such as tungsten, have been used to improve interconnection paths. Aluminum is used for the wiring, while tungsten plugs provide the interconnection between the different levels of wiring. However, the tungsten processes are complicated and expensive. Tungsten has a high resistivity, and tungsten plugs are susceptible to the presence of voids and form poor interface with the wiring layers, resulting in high contact resistance.
Copper is now being used for ULSI metallization because of its lower bulk electrical resistivity and its superior resistance to electromigration and stress voiding, as compared to commonly used aluminum and its alloys. Specifically, copper has a better electromigration property and lower resistivity than aluminum and better electrical properties than tungsten. Thus, copper is a desirable metal for use in wiring and plugs.
A typical semiconductor with copper metallization includes a copper metallization film directly deposited onto a patterned insulating film, such as SiO2 film, which is deposited on a silicon substrate and over contact holes and trenches formed in an insulating film so as to be positioned on diffused layers formed in the silicon substrate. The copper film is then polished back to leave only copper in the trenches and contact holes in accordance with a wiring pattern and then annealed at a temperature of about 400xc2x0 C. to grow grains of copper and improve electromigration resistance.
One of the problems with copper is that it is difficult to etch after deposition to form lines or via plugs. As a result, substantial time and expense is needed to etch copper. Chemical mechanical polishing has been used to polish away the unwanted copper material, but may be expensive and timely. Alternatively, copper may be selectively deposited within the vias to form plugs, which eliminates the polishing step. One technique to selectively deposit copper is electroless deposition, which requires activation of a surface to electrolessly deposit copper and is performed after placement of a barrier layer for isolation from an adjacent dielectric layer. The copper plug must also be encapsulated in the via.
Another major problem with copper is its fast diffusion in Si and drift in SiO2-based dielectrics, resulting in the deterioration of devices at low temperatures. A reaction and interdiffusion between copper in the metallization film and Si included in the substrate, or copper in the metallization film and Si in the insulating film, may occur during annealing or other heat treating processes. This reaction or interdiffusion may occur because the copper metallization film is directly in contact with the Si substrate at the through holes in the insulating film and causes an increase in contact resistance and degradation of the copper metallization. Barrier failure is caused by diffusion of copper along grain boundaries or through defects generated at elevated temperatures in the barrier films, which are relatively intact, or by the reaction between barrier films and Si forming metal-rich silicides. Thus, it is necessary to prevent the reaction and interdiffusion between Cu and Si.
A semiconductor device that addresses the problem of reaction and interdiffusion is known. This device has a silicon substrate, an insulating film in which a contact hole is formed, a metallic layer deposited on the silicon substrate through the contact hole for forming an ohmic contact to the silicon substrate, a barrier layer deposited on the metallic layer for preventing reaction and an interconnection between copper and silicon, and a metallization film including copper deposited on the barrier layer.
Another semiconductor device is known to prevent oxidation of copper at wire bonding in a pad electrode using a thin film having anti-oxidation and anti-diffusion properties. This thin film is made of metallic material, such as Ti, W, Ta, or a compound of Al2O3, TiN, TiSi2, and WSi2. In general though, transition metals are not stable diffusion barriers between copper and silicon or between copper and wire-bond metal or solder-bump metal. Adding Si to refractory materials, Ta, Mo, and W, to form an amorphous refractory metal-Si diffusion barrier improves barrier performance. A conductive metal-oxide diffusion barrier can survive thermal anneals up to between 500-600xc2x0 C. Copper-oxide tends to form at the metal-oxygen/copper interface at higher temperatures.
Another problem associated with copper interconnect is degradation in bondability for bare die stored under normal conditions. The prior art addresses this problem by storing wafers under dry nitrogen or using organic-protective coating on bond pads, but this can be expensive.
Thus, it is desirable to have a method for fabricating copper interconnect that has an improved electromigration resistance, has better performance/reliability for wire bonds, enables conventional passivation layer processes to be used, and allows wafers to be stored for extended periods of time before assembly.
The invention is a method of manufacturing an integrated circuit including the steps of: (1) providing a wafer having an inter-level dielectric film and a barrier layer; (2) depositing a seed layer of copper on the barrier layer; (3) electroplating copper to a thickness sufficient to fill in any valleys in the inter-level dielectric film and cover an entire top surface of the wafer; (4) chemical mechanical polishing the top surface to remove i) any excess portions of copper caused by the electroplating and ii) selected portions of the inter-level dielectric film; (5) depositing a layer of CrO on the polished top surface to cover remaining portions of the copper; (6) depositing a passivation layer on the layer of CrO and portions of the inter-level dielectric film; and (7) etching the passivation layer to form a via that exposes a selected portion of the layer of CrO.
Another aspect of this invention is an integrated circuit comprising a wafer having a surface, a copper layer and an interlevel dielectric film formed on selected portions of the surface, a seed layer and a barrier layer formed between the copper layer and the inter-level dielectric film, a layer of CrO deposited substantially uniformly on top of the copper layer, a passivation layer covering any exposed portions of the copper layer and the inter-level dielectric film, and a via formed in the passivation layer exposing the layer CrO.
In yet another aspect of this invention is a method of manufacturing an integrated circuit including the steps of: (1) providing a wafer having bond pads comprised of a barrier layer, a seed layer formed thereon, and copper formed on said seed layer; (2) forming a layer of CrO on the copper; (3) forming a passivation layer on the layer of CrO; and (4) etching the passivation layer to form a via that exposes the layer of CrO.
In yet another aspect of this invention is an integrated circuit including a bond pad, having a barrier layer, a seed layer formed on the barrier layer, a copper layer formed on the seed layer, and a layer of CrO covering the copper layer, formed in an inter-level dielectric film; and a passivation layer formed on any exposed portion of the copper layer, the inter-level dielectric film, and a selected portion of the layer of CrO.